The Electrostatic Discharge (ESD) is a common natural phenomenon in our lives. A large current is produced in a short time when the electrostatic discharge occurs, which causes a catastrophic failure to the integrated circuit, thus it is an important issue causing failure in the production and application of the integrated circuit. For example, the Human-Body Model (HBM) usually occurs in the hundreds of nanoseconds, the maximum peak current may reach several amperes. While in the other modes, such as Machine Model (MM), and Charged-Device Model (CDM), the electrostatic discharge occurs in much shorter time, the current is much greater. Such a large current flows through the integrated circuit in a short time, and the generated power dissipation severely exceeds the allowable maximum value, thus the integrated circuit suffers a severely physical damage to failure. The problem can be solved from the environment and the circuit in the practical application. In the environment, the main solution is to reduce the generation of static electricity and eliminate the static electricity in time; such as using the materials difficult to produce static electricity, increasing humidity, increasing operating personnel and equipment grounding and so on. In the circuit, the main solution is to increase the electrostatic discharge tolerance of the integrated circuit, such as increasing an extra-ESD protection device or circuit to protect the internal circuit of the integrated circuit from being damaged by the electrostatic discharge.
Currently, a Silicon Controlled Rectifier (SCR) is widely used in the electrostatic discharge protection circuit of the integrated circuit due to great electrostatic discharge protection and the relatively smaller device area. Generally, the parasitic SCR according to the design of the device structure in the integrated circuit can provide an electrostatic discharge protection.
U.S. Pat. No. 5,012,317 discloses an SCR applied to electrostatic discharge protection. Referring to FIG. 1, the SCR device 10 includes a P-type substrate 11, an N-type well 12 formed on the P-type substrate, a heavily doped P-type (P+) doped region 13 and a heavily doped N-type (N+) doped region 14 formed on the N-type well 12. The P+ doped region 13 and the N+ doped region 14 are connected to a contact 17 (i.e. an input of the device 10) after connecting to each other, a heavily doped N-type (N+) doped region 15 and a heavily doped P-type (P+) doped region 16 are formed on the P-type substrate and inside the N-type well, the heavily doped N-type (N+) doped region 15 and the heavily doped P-type (P+) doped region 16 are connected to a cathode (i.e. the ground terminal of the device 10) after connecting to each other. When the P-N junction between the P-type substrate 11 and the N-type well 12 is avalanched, the SCR device is turned on, the SCR current flows through the P+ doped region 14, the N-type well 12, the P-type substrate 11, and the N+ doped region 15 and releases energy to the ground terminal. The disadvantage of this structure is: when the trigger voltage is too high (approximately 60V) and the holding voltage is too low (approximately 10V), the integrated circuits with the operating voltage of 20V-40V cannot provide an effective electrostatic discharge protection, and the risk that the integrated circuit is failure due to the latch-up in practice is greatly increased.
Chinese patent 200510071001.6 discloses an electrostatic discharge device which can control the trigger voltage. Referring to FIG. 2, an electrostatic discharge device 20 formed in a P-type substrate 21, which includes an N-type well 22, a first N+ region 24c and a first P+ region 25b isolated by a field oxide, a field oxide layer 26, a second N+ region 24a, a second P+ region 25a, and a third N+ region 24b. In which, the second P+ region 25a, the N-type well 22, and the P-type substrate 21 form an equivalent transistor, while the N-type well 22, the P-type substrate 21, and the first N+ region 24c form another equivalent transistor. The field oxide layer 26 is used to isolate the third N+ region 24b and first N+ region 24c. A first electrode is connected to the second N+ region 24a and the first P+ region 25b via a first electrical conductor 28. A second electrode is connected to the second N+ region 24a and the second P+ region 25a via a second electrical conductor 27. The electrical conductors 27 and 28 can be made of metal material. In which, the predetermined distance between the edge of the second field oxide layer adjacent to the third N+ region and the edge of the N-type well is d. The trigger voltage of the electrostatic discharge device is determined by adjusting the predetermined distance. The disadvantage of this structure is that the holding voltage cannot be effectively controlled; it is unable to resolve the risk that the integrated circuit is failure due to the latch-up effect.